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M66271FP
Operation Panel Controller
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Description
The M66271FP is a graphic display-only controller for displaying a high duty dot matrix type LCD which is used widely for PPC, FAX and multi-function telephones. It is capable of controlling a monochrome STN LCD system of up to 320 x 240 dots. The IC has a built-in 9600-byte VRAM as a display data memory. All of the VRAM addresses are externally opened. Address mapping in the MPU memory space allows direct addressing of all display data from the MPU, thus providing efficient display data processing such as drawing. The built-in arbiter circuit (cycle steal system) which gives priority to display access allows timing-free access from MPU to VRAM, preventing display screen distortion. The IC provides interface with a 8-bit/16-bit MPU with a READY (WAIT) pin. And this IC has a function for LCD module built-in system by lessening connect pins between MPU.
Features
* Displayable LCD Monochrome STN dot matrix type LCD of up to 76800 dots (equivalent to 320 x 240 dots) Maximum display duty: 1/240 (set to 240 line) : 1/255 (Max) * Display memory Built-in 9600-byte (76800-bit) VRAM (equivalent to one screen of 320 x 240 dots LCD) All addresses of built-in VRAM are externally opened. * Interface with MPU Capability of switching 8-bit type MPU/16-bit type MPU With WAIT output pin (Accessing register from MPU without WAIT output. Accessing VRAM from MPU with WAIT output.) Capability of controlling BHE or LWR/HWR at the interface with a 16-bit MPU. * Interface with LCD LCD display data are 4-bit parallel output 4 kinds of control signals: CP, LP, FLM and M * Display functions Graphic display only (characters drawn graphically) Binary display only (without tone display function) Vertical scrolling is allowed within memory range (small size LCD only) * Additional function for LCD module built-in system 15 kinds of interface with MPU: A <4:1>, D <7:0>, IOCS, LWR, RD Accessing VRAM from MPU through I/O register Capability of interfacing with 8-bit type MPU only * 5 V single power supply * 80-pin QFP
Application
* * * * PPC/FAX operation panel, display/operation panel of other OA equipment Multi-function/public telephones PDA/electronic notebook/information terminal Other applications using LCD of 76800 dots or less
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 1 of 27
M66271FP
Block Diagram 1
VDD
8 23 34 42 52 53 77
15
:
MPU address bus
A <13:0>
22 26
:
31
Address buffer
61
LCDENB CP LP FLM M
LCD control signal Display data transfer clock Display data latch pulse First line marker signal LCD alternating signal
Control register
66
LCD display timing control circuit
67
68
62
43
:
MPU data bus
D <15:0>
50 53
Data buffer
:
60
VRAM
Control register chip select VRAM chip select
IOCS MCS High write strobe HWR Low write strobe LWR Read strobe RD 8/16 MPU select MPUSEL Reset RESET Bus high enable BHE MPU clock MPUCLK Wait WAIT
2
6
3
4
5
12
11
14
9
7
9600-byte
LCD display data control circuit
69
70
71
72
UD <3:0> data bus
LCD display
MPU I/F control circuit
Bus arbiter timing control Clock control
(Basic timing control)
1 10 13 24 25 35 40 41 51 64 65 80
32 33 36 37 38 39 73 74 75 76
Oscillator input Oscillator output
OSC1 OSC2
78
79
(Cycle steal control)
VSS
N.C
Block Diagram 2 (In case of LCD module built-In system)
No use pins
3 20 6 7 22 9 26 11 12 14 15 8
VDD
23 34 42 52 63 77
_
_
31
53
_
60
MPU address bus
16
A <4:1>
:
19
Address buffer
61
LCDENB CP LP FLM M
Control register
66
LCD display timing control circuit
67 68 62
LCD control signal Display data transfer clock Display data latch pulse First line marker signal LCD alternating signal
MPU data bus D
<7:0>
43
:
50
Data buffer
VRAM address index register Data port register
VRAM 9600-byte
LCD display data control circuit
69 70 71 72
Control register chip select
IOCS
2
UD <3:0>
LCD display data bus
Low write strobe Read strobe
LWR RD
4 5
MPU I/F control circuit
Oscillator input Oscillator output
OSC1 OSC2
78 79
Clock control
(Basic timing control)
1
Bus arbiter timing control
10 13 24 25 35 40 41 51 64 65 80
32 33 36 37 38 39 73 74 75 76
VSS
N.C
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 2 of 27
M66271FP
Display data transfer clock
Display data latch pulse First line marker
LCD display data bus
Oscillator input
77 66 78 76 75 74 73 72 71 70 69 68 67 65
Pin Arrangement
Oscillator output
VSS CP LP FLM UD <0> UD <1> UD <2> UD <3> N.C N.C N.C N.C VDD OSC1 OSC2 VSS
80
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
79
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
VSS
Control register chip select High write strobe Low write strobe Read strobe VRAM chip select Wait MPU clock Reset 8/16 MPU select Bus high enable
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 3 of 27
IOCS HWR LWR RD MCS WAIT VDD MPUCLK VSS RESET MPUSEL VSS BHE
M66271FP
(Top view)
MPU address bus
A <0> A <1> A <2> A <3> A <4> A <5> A <6> A <7> VDD VSS
24
VSS VDD LCD alternating signal M LCDENB LCD control signal D <15> D <14> D <13> D <12> MPU data bus D <11> D <10> D <9> D <8> VDD VSS D <7> D <6> D <5> D <4>
MPU data bus
Outline: PRQP0080GB-A (80P6N-A)
25 26
41
D <3> D <2> D <1> D <0> VDD VSS
33 27 28 29 30 31 32 34 35 36 37 38 39 40
N.C: No connection
VSS N.C N.C N.C N.C VSS VDD N.C N.C A <13> A <12> A <11> MPU address bus A <10> A <9> A <8> VSS
M66271FP
Pin Description
Item MPU interface Pin Name D <15:0> Input/ Output Input/ Output Input Function MPU data bus Connect to MPU data bus. Selecting 8-bit MPU by MPUSEL input, D <15:8> connect to VDD or VSS MPU address bus Connect to MPU address bus. When selecting 8-bit MPU, use A <13:0>. And selecting16-bit MPU, use A <13:1> for the address bus with combining A <0> and BHE by the method of access to internal VRAM (Refer to figure 1). Use A <4:0> for selecting address of control register. Chip select input of control register When this pin is "L", select the internal control register. Assign to I/O space of MPU. Chip select input of VRAM When this pin is "L", select the internal VRAM. Assign to memory space of MPU. High-write strobe input When this pin is "L", data write to the internal VRAM. HWR is valid only in using 16bit MPU controlled byte access by LWR and HWR. (Refer to figure 1) Low-write strobe input When this pin is ''L", data write to the internal control register or VRAM. (Refer to figure 1) Read strobe input When this pin is "L", data read from the internal control register or VRAM. (Refer to figure 1) 8/16-bit MPU select input According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU Reset input Use reset signal of MPU. When this pin is "L", initialize all internal control register and counter. MPU clock Input of MPU clock. Bus-high-enable input This pin is valid when using 16-bit MPU controlled byte access by A <0> and BHE (Refer to figure 1). Connect to "VDD" when using 8-bit MPU. Set to ''L'' when using the additional function for the LCD module built-in system. WAIT output for MPU This signal makes WAIT for MPU. Change WAIT ''L'' at timing of falling edge of overlapping with MCS and (RD or LWR or HWR). And return to "H" at synchronizing with the rising edge of MPUCLK after internal processing. (Output WAIT only when requested access from MPU to VRAM during cycle steal access.) Display data bus for LCD Transfer the LCD display data with 4-bit parallel signal. Mutually output upper/lower data every CP output. Display data transfer clock Shift clock for the transfer of display data to LCD. Take the display data of UD <3:0> to LCD at falling edge of CP. Display data latch pulse This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal. LP output when finish the transfer of display data of a line. Latch of display data and the transfer of scanning signal at falling edge of LP. First line marker signal Output the start pulse of scanning line. This signal is "H" active, the IC for driving scanning line catch FLM at falling edge of LP. LCD alternating signal output Signal for driving LCD by alternating current. LCD (ON/OFF) control signal output Output data which is set at bit "0" of mode register (R1) in control register. This signal can use for controlling the LCD power supply, because LCDENB set to "L" by RESET. Input pin for oscillator Generate an internal clock. For crystal oscillator or external clock signal. Output pin for oscillator Power supply (source + 5 V) Ground No connection Number of Pins 16
A <13:0>
14
IOCS MCS HWR LWR RD MPUSEL RESET MPUCLK BHE
Input Input Input
1 1 1
Input
1
Input
1
Input Input
1 1
Input Input
1 1
WAIT
Output
1
LCD interface
UD <3:0>
Output
4
CP
Output
1
LP
Output
1
FLM
Output
1
M LCDENB
Output Output
1 1
Oscillator Others
OSC1 OSC2 VDD VSS N.C
Input Output -- -- --
1 1 7 12 10
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 4 of 27
M66271FP
Absolute Maximum Ratings
(Ta = 0 to +70C unless otherwise noted)
Item Supply voltage Input voltage Output voltage Output current Power dissipation Storage temperature VDD VI VO IO Pd Tstg Symbol Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 10 600 -55 to +150 Unit V V V mA mW C
Recommended Operating Conditions
(Ta = 0 to +70C unless otherwise noted)
Item Supply voltage Supply voltage Input voltage Output voltage Operating temperature Symbol VDD VSS VI VO Topr Min 4.5 -- 0 0 0 Typ 5.0 0 -- -- +25 Max 5.5 -- VDD VDD +70 Unit V V V V C
Electrical Characteristics
(VDD = 5 V 10%, Ta = 0 to +70C unless otherwise noted)
Item High-level input voltage All inputs except for OSC1, RESET and Low-level input voltage MPUSEL High-level input voltage Low-level input voltage Positive-going threshold voltage Negative-going threshold voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage High-level input current Low-level input current Off-state high-level output current Off-state low-level output current Operating supply current (Average) OSC1 MPUSEL, RESET Symbol VIH VIL VIH VIL VT+ VT- All outputs except for OSC2 and outputs of D <15:0> OSC2 VOH VOL VOH VOL IIH IIL IOZH IOZL IDD (A) Min 2.2 -- 3.5 -- 2.3 1.25 4.1 -- 4.1 -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- 0.8 -- 1.0 3.7 2.3 -- 0.4 -- 0.4 10 -10 10 -10 40 Unit V V V V V V V V V V A A A A mA VDD = 4.5 V Test Conditions VDD = 5.5 V VDD = 4.5 V VDD = 5.5 V VDD = 4.5 V VDD = 5.0 V VDD = 5.0 V VDD = 4.5 V IOH = -4 mA IOL = 4 mA IOH = -50 A IOL = 50 A VDD = 5.5 V, VI = VDD VDD = 5.5 V, VI = VSS VDD = 5.5 V, VO = VDD VDD = 5.5 V, VO = VSS VDD = 5.5 V, VI = VDD or VSS fosc = 10 MHz, Output = open VDD = 5.5 V, IOCS, MCS = VDD Other's VI = VDD or VSS (valid)
D <15:0>
Stand-by supply current
IDD (S)
--
--
500
A
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 5 of 27
M66271FP
Switching Characteristics
(VDD = 5 V 10%, Ta = 0 to +70C, CL = 50 pF)
Item IOCS data access time MCS data access time RD data access time Output disable time after IOCS Output disable time after MCS Output disable time after RD WAIT output propagation time after MCS WAIT output propagation time after WR WAIT output propagation time after RD WAIT output propagation time after MPUCLK CP output propagation time after OSC LP output propagation time after OSC UD access time FLM output propagation time after OSC M output propagation time after OSC LCDENB output propagation time after OSC Data definite time before canceling WAIT Symbol ta (IOCS-D) ta (MCS-D) ta (RD-D) tdis (IOCS-D) tdis (MCS-D) tdis (RD-D) tpHL (MCS-WAIT) tpHL (WR-WAIT) tpHL (RD-WAIT) tpLH (CLK-WAIT) tpd (OSC-CP) tpLH (OSC-LP) tpHL (OSC-LP) ta (UD) tpLH (OSC-FLM) tpHL (OSC-FLM) tpd (OSC-M) tpLH (OSC-LE) tpHL (OSC-LE) tpd (D-WAIT) Min -- Typ -- Max 70 Unit ns
--
--
20
ns
--
--
40
ns
-- -- -- -- -- -- -- 0
-- -- -- -- -- -- -- --
20 40 40 40 40 40 40 --
ns ns ns ns ns ns ns ns
Timing Requirements
(VDD = 5 V 10%, Ta = 0 to +70C) (1) Accessing to Control Register
Item IOCS pulse width LWR pulse width Data set up time before falling edge of IOCS Data set up time before falling edge of LWR Data hold time after rising edge of IOCS Date hold time after rising edge of LWR Address set up time before falling edge of IOCS Address set up time before falling edge of LWR Address set up time before falling edge of RD Address hold time after rising edge of IOCS Address hold time after rising edge of LWR Address hold time after rising edge of RD Symbol tW (IOCS) tW (LWR) tsu (D-IOCS) tsu (D-LWR) th (IOCS-D) th (LWR-D) tsu (A-IOCS) tsu (A-LWR) tsu (A-RD) th (IOCS-A) th (LWR-A) th (RD-A) Min 70 0 15 15 Typ -- -- -- -- Max -- -- -- -- Unit ns ns ns ns
15
--
--
ns
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 6 of 27
M66271FP (2) Accessing to VRAM
Item MCS pulse width WR pulse width Data set up time before falling edge of MCS Data set up time before falling edge of WR Data hold time after rising edge of MCS Data hold time after rising edge of WR Address set up time before falling edge of MCS Address set up time before falling edge of WR Address set up time before falling edge of RD Address hold time after rising edge of MCS Address hold time after rising edge of WR Address hold time after rising edge of RD Symbol tW (MCS) tW (WR) tsu (D-MCS) tsu (D-WR) th (MCS-D) th (WR-D) tsu (A-MCS) tsu (A-WR) tsu (A-RD) th (MCS-A) th (WR-A) th (RD-A) Min 70 0 15 15 Typ -- -- -- -- Max -- -- -- -- Unit ns ns ns ns
15
--
--
ns
(3) Clock and Accessing to LCD Display
Item MPUCLK cycle time MPUCLK "H" pulse width MPUCLK "L" pulse width OSC cycle time OSC "H'' pulse width OSC "L" pulse width CP cycle time CP "H" pulse width CP "L" pulse width FLM pulse width Note: Symbol tC (CLK) tWH (CLK) tWL (CLK) tC (OSC) tWH (OSC) tWL (OSC) tC (CP) tWH (CP) tWL (CP) tW (FLM) Min 50 -- 50* -- -- -- -- Typ -- tC (CLK) 2 -- tC (OSC) 2 tC (OSC) (1/n) tC (OSC) 2 * (1/n) 2 * tC (OSC) * LPW (1/n) Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
Clock frequency of OSC1 input is less than fmax = 20 MHz. Limit of OSC clock for the internal operation is fmax = 10 MHz. When OSC1 is more than 10 MHz from external input, set OSC clock up to 10 MHz by using division of OSCC register. Division is set with rising edge of OSC1 input. 1/n = Division of OSC1 LPW = Setting value of LPW register
Test Circuit
VDD
Item
RL = 1 k SW1
SW1 Closed Open Closed Open
SW2 Open Closed Open Closed
Input
VDD
D <15:0>
SW2
tdis (LZ) tdis (HZ) ta (ZL) ta (ZH)
P.G
50
DUT
CL RL = 1 k
(1) Input pulse level: 0 to 3 V Input pulse rise/fall time: tr, tf = 3 ns Input decision voltage: 1.5 V
Outputs except for D <15:0>
Output decision voltage: VDD/2 (However, tdis (LZ) is 10% of output amplitude and tdis
(HZ)
VSS
CL
is 90% of that for decision.)
(2) Load capacity CL include float capacity of connection and input capacity of probe.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 7 of 27
M66271FP
Outline
M66271FP is graphic display only controller for displaying a dot matrix type LCD. This IC has a built-in display data memory (VRAM) which is equivalent to 320 x 240 dots LCD. * Control register When access the control register from MPU side, use IOCS, LWR, RD, A <4:0> and D <7:0>. Refer to table 1, when set control type inputs. Control registers are R1 to R8 for the normal mode function and R9 to R11 for the exclusive register for the LCD module built-in system. * VRAM When access VRAM from MPU side, use MCS, HWR, LWR, RD, BHE, A <13:0> and D <15:0>. And enable to correspond to both 8-bit and 16-bit MPU by using MPUSEL input. Refer to figure 1 and table 2 to 6 for a form of VRAM and input setting for 8/16-bit MPU. * Cycle steal system Cycle steal is interact method of transferring display data for LCD from VRAM and accessing VRAM from MPU on the basic cycle of OSC. Basic timing is two clocks of OSC, and assign first clock to the access from MPU to VRAM and second clock to the transfer of display data from VRAM to LCD. In accessing VRAM from MPU, output WAIT. Change WAIT to "L" at the timing of the falling edge of overlapping with MCS and (RD or LWR/HWR). And return to "H" at synchronizing with rising edge of MPUCLK after internal processing. Cycle steal system can transfer data with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of MPU during horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. Refer to the following description of cycle steal. * Output to LCD side LCD display data UD <3:0> output synchronized with the rising edge of CP output per 4 bits. LP output synchronized with the falling edge of OSC when finish the transfer of display data for a line. Enable to adjust the fittest value of the frame frequency requested by the LCD PANEL side with adjusting pulse width by LPW register. FLM output, when finish the transfer of display data of 1st line. M output is the LCD alternating signal which is signal for driving LCD by alternating current. M-cycle enable to set variably by M-cycle variable register in line unit, and enable to utilize for preventing LCD from being inferior.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 8 of 27
M66271FP Difference in VRAM between 8-bit and 16-bit MPU
(1) When accessing built-in VRAM by 8-bit MPU
(MPUSEL = "L", BHE = "H", HWR = "H": set)
A <13:0> MCS LWR D <7:0> RD
A <13:0> CEC
VRAM
WEC DI <7:0> DO <7:0>
9600-byte
(2) When accessing built-in VRAM by 16-bit MPU
(2-1) In case MPU use A <0> and BHE for byte access (MPUSEL = "H", HWR = "H": set)
(2-2) In case MPU use LWR and HWR for byte access (MPUSEL = "H", BHE = "H", A <0> = "H": set)
A <13:1>
A <0>
A <13:1> A <0> CEC WEC DI <7:0> DO <7:0>
A <13:1>
VRAM 4800-byte (Lower byte)
A <13:1>
MCS LWR D <7:0>
MCS LWR D <7:0>
VRAM
CEC WEC DI <7:0> DO <7:0>
4800-byte (Lower byte)
A <13:1>
A <13:1>
BHE
A <0>
VRAM
CEC CEC
VRAM
4800-byte
WEC
D <15:8> RD
(Upper byte)
DI <15:8> DO <15:8>
HWR D <15:8> RD
4800-byte
WEC DI <15:8> DO <15:8>
(Upper byte)
Figure 1 Difference in VRAM between 8-bit and 16-bit MPU
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 9 of 27
M66271FP
Combination of Control Input Pins for MPU Interface
Table 1 to 6 show conditions of input setting when access the control register and VRAM from MPU. (1) Access control register (Use address = A <4:0>, Data = D <7:0>) Table 1
IOCS L L H LWR L H X RD H L X Operation Write to control register Read from control register Invalid
(2) Writing to VRAM (2-1) When use 8-bit MPU (MPUSEL = "L", BHE = HWR = "H": set) Table 2
MPU SEL L MCS L BHE H A <0> L H X X HWR H LWR L H X Odd Address Invalid Write Invalid Even Address Write Invalid Invalid Valid Data Bus Width of MPU 8-bit
H
(2-2) When use 16-bit MPU (In MPU controls byte access with A <0> and BHE, MPUSEL = HWR = "H": set) Table 3
MPU SEL H MCS L BHE L A <0> L H H L H H X X HWR H LWR L H L H L H L H X Upper Byte Write Invalid Write Invalid Invalid Invalid Invalid Invalid Lower Byte Write Invalid Invalid Invalid Write Invalid Write Invalid Valid Data Bus Width of MPU 16-bit Upper 8-bit Lower 8-bit Lower 8-bit Even if A <0> = "H", enable to write
(2-3) When use 16-bit MPU (In MPU controls byte access with LWR and HWR, MPUSEL = BHE = A <0> = "H": set) Table 4
MPU SEL H MCS L BHE H A <0> H HWR L H H X LWR L H L H X Upper Byte Write Write Invalid Invalid Lower Byte Write Invalid Write Invalid Valid Data Bus Width of MPU 16-bit Upper 8-bit Lower 8-bit
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 10 of 27
M66271FP (3) Reading from VRAM (3-1) When use 8-bit MPU (MPUSEL = "L", BHE = "H": set) Table 5
MPU SEL L MCS L BHE H A <0> L H X RD L H X Odd Address Invalid Read Invalid Even Address Read Invalid Invalid Valid Data Bus Width of MPU 8-bit
H
(3-2) When use 16-bit MPU (MPUSEL = ''H": set) Table 6
MPU SEL H MCS L H Note: BHE X A <0> X RD L H X Upper Byte Read Invalid Lower Byte Read Invalid Valid Data Bus Width of MPU 16-bit
Avoid setting combination except above, as cause of error action. X = "L" or "H''
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 11 of 27
M66271FP
Description of Cycle Steal
Basic Timing Basic timing of M66271FP is two clocks of OSC (internal clock after dividing OSC1 input). Assign first clock to accessing from MPU to VRAM and second clock to transferring of display data from VRAM to LCD.
Access from MPU to VRAM Data transfer from VRAM to LCD
MPU
LCD
OSC
(Internal clock after dividing OSC1 input)
CP output
(Display data transfer)
Basic cycle
Figure 2 Basic Timing
Operation Cycle of MPU Access (During WAIT Output) Writing or reading operation for VRAM during cycle steal needs 1 cycle in best case or 3 cycles in worst case, according to the condition of the internal cycle steal at staring access requested from MPU.
Ex.) Assuming that MCS input is later than RD, LWR and HWR input.
Best case
MCS WAIT
Cycle of LCD access
Cycle of MPU access
Cycle of LCD access
Cycle of MPU access
Cycle of LCD access
Cancel WAIT, when synchronize with rising edge of MPUCLK
MPUCLK
Worst case
MCS
WAIT
Cancel WAIT, when synchronize with rising edge of MPUCLK
MPUCLK
Figure 3 Operation Cycle of MPU Access
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 12 of 27
M66271FP Function of Cycle Steal Control M66271FP has a function for processing data of a line with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On other side, don't output WAIT for keeping throughput of MPU during the horizontal synchronous term with no necessity for the display data transfer from VRAM to LCD side. But certainly set a term of accessing with the cycle steal method by CSW register, for controlling an error action near the end of horizontal synchronous term.
Ex.) Assuming 320 x 240 dots LCD
1 Line
LP
1 2 3 78 79
80
Output when finish transfer of display data with a line
1
CP UD <3:0>
Setting by CR register Displaying term (Cycle steal method) (Necessity for data transfer from VRAM to LCD side) Setting by LPW register Horizontal synchronous term (No necessity for data transfer from VRAM to LCD side)
Output every transfer of a display data
4-bit transfer
CSE
(Internal signal)
Setting by CSW register
Start WAIT for MPU according to cycle steal access
Access with bus timing of MPU without WAIT for MPU.
Start WAIT for MPU in timing of CSE "H" according to bus timing of MPU
Figure 4 Function of Cycle Steal Control
Handling of Oscillator Pin
<1> Crystal oscillator <2> Input from external clock directly
Crystal oscillator OSC1 C1 Rf Rd
M66271FP
Clock generator
OSC1
M66271FP
OSC2 C2
Open
OSC2
Note: As far as possible, connect C, R and the crystal oscillator at near the pin.
Figure 5 Oscillator Pin
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 13 of 27
M66271FP Additional Function for LCD Module Built-in System As all of the VRAM address in M66271FP are externally opened for addressing VRAM from MPU directly. When consider the LCD module built-in system, connect pins are increased. But M66271FP has an additional function for the LCD module built-in system by lessening connect pins. Outline of the additional function for the LCD module built-in system. * Interface pins with MPU 15 kinds of interface with MPU: A <4:1>, D <7:0>, IOCS, LWR, RD * Method of accessing the internal VRAM Access the internal VRAM through the VRAM address index register (IDXL, IDXH) and the data port register (DP) which are used for I/O register. The following show the process of accessing VRAM.
Setting to MPUSEL, BHE = "L"
No use pins set the following. HWR = "H", MCS = "H", WAIT = open, MPUCLK = "L", MPUSEL = "L", BHE = "L", A <0> = "L", A <13:5> = "L", D <15:8> = "L", RESET = Power on reset or soft ware reset. (In case of soft ware reset RESET = "H": set) Enable to change IDXL and IDXH, even if either.
Select VRAM address index register (IDXL, IDXH), and write access address (14-bit) as data.
Access the DP after writing the mode register (DISP (R1 - D2)) = "0". Always enable to access (CSES register = "0"), because the display signal fix "H" or "L" in DISP = "0" and a term is no wait access. Access DP without WAIT function.
Select Data port register (DP). Reading/Writing data for appointed VRAM address.
VRAM address is increased of +1.
VRAM address is automatically increased of +1, when finished access to DP. When access to continuous address, it doesn't need to set IDXL and IDXH.
Application
MPU side A <4:1> D <7:0> IOCS LWR RD
M66271FP Segment driver
LCD side
Common driver Graphic LCD PANEL
Crystal Oscillator
Note: LCD module of small size for only graphics
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 14 of 27
M66271FP Control Register M66271FP has 9 kinds of control register. To set mode from MPU to control register, use IOCS, LWR, RD, A <4:0> and D <7:0>. (1) Kind of control register Control Register Table
Kind of Register No. R1 Name Mode register Horizontal display character number register Horizontal synchronous pulse width register Cycle steal enable width register Vertical line number register Display start address register A4 0 Address A3 0 A2 0 A1 0 A0 0 D7
CSES
Data D6
RESET
D5
D4
D3
D2
DISP
D1
REV
D0
LCDE
Functions of Register D6 to D0 set the basic mode. D7 is the status register of cycle steal state. Set the number of horizontal display characters per line.
R/W R/W
D7 = Only "R"
- OSCC -
R2
W
0
0
0
1
0
--------- CR ------------
R3
0
0
1
0
0
-------------- LPW -----------------
Set the pulse width of LP per line.
W
R4
0
0
1
1
Set the term of cycle steal 0 -------------- CSW ---------------- enable access during horizontal synchronous term. Set the number of display line 0 --------------- SLT ------------------ of vertical direction. Set the display start address 0 --------------- SAL ---------------- of VRAM. Set lower 8-bit to SAL and 0 ---------- SAH ----------- upper 6-bit to SAH. Max = 257FH Set the cycle of LCD 0 ---------------- MT ----------------- alternating signal from M. Data port register for 0 ---------------- DP ----------------- accessing VRAM through the register. Set the address for accessing 0 ---------------- IDXL ---------------- VRAM. Set lower 8-bit to IDXL and upper 6-bit to IDXH. Max = 257FH 0 --------- IDXH ----------- And automatically increase in continuous address.
W
R5
W
0
1
0
0
R6
R/W
0
1
0
1
R7
0 R8 M cycle variable register Data port register VRAM address index register
1
1
0
W
0
1
1
1
R9
R/W
1
0
0
0
R10
R/W
1
0
0
1
R11 1 0 1 0
Note:
Data port register (DP) and VRAM address index register (IDXL, IDXH) are exclusive register, when using this IC for the LCD module built-in system. When RESET, each register is initialize the setting which is assumed LCD size of 320 x 240 dots. Then, even if each register has not setting, output the signal to LCD side, it is possible to be alternation of LCD.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 15 of 27
M66271FP (2) Description of register (2-1) Mode register [R1]
Address 00000 R/W D7 = Only "R" D7 0 1 CSES No wait access Cycle steal access R/W Function Reset 0
* * * * *
Status register for identifying active or inactive in cycle steal function. Set "1" during active with cycle steal function. CSES is for only reading, not for writing.
Software reset. Surely return to reset off after reset on.
0
D6 0 1 Reset OFF Reset ON
RESET
*
OSCC D5 0 0 0 0 1 D4 0 0 1 1 0 D3 0 1 0 1 0 Division of OSC1 1 1/2 Division 1/4 Division 1/8 Division 1/16 Division
Set the division of OSC clock for internal operation from OSC1 input pin.
000
* *
When reset, OSCC = 000, OSC1 clock doesn't divide. Don't set except left table.
D2 0 1
DISP Display OFF Display ON
* * *
Control the displaying ON/OFF of LCD. When reset, DISP = 0, set display OFF. REV (D1) set "1", and when DISP = "0" display data UD <3:0> output "1" in reversal mode.
0
D1 0 1
REV Normal display Reversal display
* * *
Control normal/reversal of LCD display. When reset, REV = 0, set normal display. In using LCD of permeation method, REV = "1" has effect.
0
D0 0 1
LCDE LCDENB = "0" output LCDENB = "1" output
* * *
Set the output data from LCDENB output pin. When reset, LCDE = 0, LCDENB output "0" (Vss potential). This function is prepared for controlling the voltage of LCD. When the power supply is ON after finish each register setting, LCDE = "1", supply voltage of LCD. Conversely for setting power supply OFF, first LCDE = "0", the voltage of LCD is OFF. Therefore enable to prevent LCD from being unusual voltage as DC. This function use for satisfy the need of LCD.
0
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 16 of 27
M66271FP (2-2) Horizontal display characters number register [R2]
Address 00010 R/W W CR D7 D6 D5 0 0 0 1 D4 0 0 0 1 D3 0 0 0 1 1 1 1 D2 0 0 0 D1 0 0 1 D0 0 1 0 Character Number -- 1 2 63 Display Dot Number -- 8 16 504 Function Reset 28H
* *
Note:
The number of horizontal display characters per line can set to the extent of Max = 504 dots (= 63 characters) When reset, CR = "28H" (= 40 characters = 320 dots)
Definition of the number of display characters. The number of display characters means data which is corresponding with 1 byte of VRAM. In case of binary, 1 bit of VRAM corresponds to 1 dot of display, then 1 character means 8 dots of display.
(2-3) Horizontal synchronous pulse width register [R3]
Address 00100 R/W W LPW D7 0 0 0 1 D6 0 0 0 1 D5 0 0 0 1 D4 0 0 0 1 1 1 1 1 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 Character Number -- 1 2 255 Function Reset 01H
*
Set the length of horizontal synchronous pulse width which appeared per line in character unit. Horizontal synchronous pulse output from LP output pin, and use for changing serial/parallel of displaying data. Adjusting this pulse width is possible to set frame frequency the fittest value. And the actual LP output pulse is (LPW setting value - 1CP) in consideration of timing with CP output.
*
When reset, LPW = "01H" (= 1 character)
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 17 of 27
M66271FP (2-4) Cycle steal enable width register [R4]
Address 00110 R/W W CSW D7 0 0 0 1 D6 0 0 0 1 D5 0 0 0 1 D4 0 0 0 1 1 1 1 1 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 Character Number -- 1 2 255 Function Reset 00H
*
During the horizontal synchronous term, set term of access by cycle steal method in character number unit. Setting value of CSW sets below LPW value. When reset, CSW = "00H"
*
Note:
Be careful with first and second byte of display data UD <3:0> output indefinite data when setting value of CSW is still reset (00H). Surely CSW set over 01H. (When select 8-bit MPU, 1 byte is indefinite. When 16-bit and SAL: D <0> = 0, 2 byte are indefinite. When 16-bit and SAL: D <0> = 1, 1 byte is indefinite.)
(2-5) Vertical line number register [R5]
Address 01000 R/W W SLT D7 0 0 0 1 D6 0 0 0 1 D5 0 0 0 1 D4 0 0 0 1 1 1 1 1 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 Vertical Line Number -- 1 2 255 Function Reset F0H
* * *
SLT combine the setting of display driving duty of LCD. Setting of SLT is sure to adjust to the number of display line of LCD. When reset, SLT = "F0H" (= 240 lines).
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 18 of 27
M66271FP (2-6)
Address 01010 SAL
D7 D6 D5 0 0 0
Display start address register [R6, R7]
R/W R/W
SAH D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 0 0 D7 0 0 0 D6 0 0 0 D5 0 0 0 SAL D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 Display Start Address 0000H 0001H 0002H
Function
Reset 0000H
1 0 0 1 0 1 0 1 1 1
1 1 1 1
257FH
01100 SAH
* * * * * * *
D6 and D7 output "0" when read SAH. It is possible to set display start address to the extent of 257FH (= 9600 address). Don't set over 2580H. When reset, SAL and SAH = "0000H" Display start address is established by the writing data to SAH register. Even if only change SAL, surely set SAH after SAL. When select 8-bit MPU, start address set in SAL + SAH . When select 16-bit MPU, start address set in SAL + SAH . Even it selecting 16-bit MPU, enable to set display start address in character unit. In case the display reading data from VRAM start at D <15:12>, set SAL = "0", and if start at D <7:4>, set SAL = "1". (Refer to figure 8)
(2-7) M cycle variable register [R8]
Address 01110 R/W W MT D7 0 0 0 1 D6 0 0 0 1 D5 0 0 0 1 D4 0 0 0 1 1 1 1 1 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 Cycle of M Toggle change at every 1 frame. Toggle change at every 1 line (1LP). Toggle change at every 2 lines. Toggle change at every 255 lines. Function Reset 00H
* * *
Set the cycle of M. In case of MT = 01H, M repeat reversal (toggle) at every 1 line (at every 1 count of LP). When reset, MT = "00H", toggle M signal at every 1 frame. We recommend this register set suitable value for user's LCD.
(2-8) Data port register [R9]
Address 10000 R/W R/W DP D7 D6 D5 D4 D3 D2 D1 D0 Data Port (8-bit) Function Reset XXH (indefinite)
* * *
Exclusive data port register for the LCD module built-in system. Reading or writing 8-bit data between MPU and VRAM through this register. VRAM address index register (IDXL, IDXH) is increased of +1, when finished access to DP. Output indefinite data when reset.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 19 of 27
M66271FP (2-9) VRAM address index register [R10, R11]
Address 10010 IDXL
D7 D6 D5 0 0 0
R/W R/W
IDXH D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 0 0
Function
Reset 0000H
IDXL Accessing D2 0 0 0 D1 0 0 1 D0 0 1 0 VRAM Address 0000H 0001H 0002H 1 1 1 1 257FH
D7 0 0 0
D6 0 0 0
D5 0 0 0
D4 0 0 0
D3 0 0 0
10100 IDXH
1
0
0
1
0
1
0
1
1
1
* * * * * *
Exclusive VRAM address index register for the LCD module built-in system. It is possible to change the register only one side, because IDXH and IDXL are independent each other. It is possible to set VRAM access address to the extent of 257FH (= 9600 address). Don't set address over 2580H. D6 and D7 output "0" when read IDXH When reset, IDXL and IDXH = "0000H".
Description of LCD Display
Relation between Setting of Control Register and LCD Displaying
1 horizontal line
CR
LPW
CSW
Expectant LCD PANEL
SLT
Condition of control register (CR x 8) x SLT 76800 dots
1 horizontal line
CR Character number of horizontal display
LPW Horizontal synchronous pulse width
x Vertical line number SLT
OSC
1 2 3 n-2 n-1 n 1
2
CP UD <3:0>
1 Character number = 8 dots display Data is indefinite
LP
(1) Time for processing a horizontal line (TH) 2 TH = x (CR + LPW)
fosc
CR, LPW, CSW: Unit of character number SLT: Unit of line number fosc: Internal OSC clock frequency after dividing OSC1 input
By adjusting LPW, it is possible to set a frame frequency which is requested from LCD PANEL the fittest value.
(2) Time for processing a frame (TFR)
TFR = TH x SLT
Figure 6 Relation between Setting of Control Register and LCD Displaying
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 20 of 27
M66271FP Relation between Address of VRAM and LCD Display
ex. 1) When display start address = 0000H
0000H 0001H
VRAM address mapping on the LCD PANEL
0000H 0001H
VRAM 9600-byte
257EH 257FH
LCD PANEL
257EH 257FH CR 8 dots
SLT line
ex. 2) When display start address = 1000H
0000H 0001H 1000H 1001H
VRAM 9600-byte
1000H 1001H
LCD PANEL
257EH 257FH 0000H 0001H
257EH 257FH
Remark) VRAM address counter return to "0000H", after count up address to "257FH".
Figure 7 Relation between Address of VRAM and LCD Display
Relation between VRAM Data, LCD Display and Display Start Address Register
(1) When select 8-bit MPU
UD3 D7 1 UD2 D6 0 UD1 D5 1 UD0 D4 0 UD3 D3 0 UD2 D2 1 UD1 D1 0 UD0 D0 1
LCD display data Data of one address for VRAM
LCD PANEL
(2) When select 16-bit MPU (SAL: D0 = "0")
UD3 D15 1 UD2 D14 0 UD1 D13 1 UD0 D12 0 UD3 D11 0 UD2 D10 1 UD1 D9 0 UD0 D8 1 UD3 D7 0 UD2 D6 0 UD1 D5 0 UD0 D4 0 UD3 D3 1 UD2 D2 1 UD1 D1 1 UD0 D0 1
LCD display data Data of one address for VRAM
LCD PANEL
(3) When select 16-bit MPU (SAL: D0 = "1")
Invalid display data
D15 1 D14 0 D13 1 D12 0 D11 0 D10 1 D9 0 D8 1 UD3 D7 0 UD2 D6 0 UD1 D5 0 UD0 D4 0 UD3 D3 1 UD2 D2 1 UD1 D1 1 UD0 D0 1
LCD display data Data of one address for VRAM
LCD PANEL
* Only upper byte data of the display start address is invalid data (cut off data). * Output the display data normally from next address of the display start address.
Figure 8 Relation between VRAM Data, LCD Display and Display Start Address Register
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 21 of 27
M66271FP Output Signal of LCD Side
Ex.) Assuming 320 x 240 dots LCD (In setting of CR = 40 characters, LPW = 2 characters, SLT = 240 lines, OSCC = 1 division, MT = 1 toggle per line)
(1) Output signal per line
OSC1
80 1 2 79 80 1 2
Division of OSC1 = 1 Output every display data transfer
CP UD <3:0> LP
(2) Output signal per frame
239 240 1
4-bit parallel output Output when finish the transfer of one line of display data.
239
240
1
LP FLM M
(3) LCDENB output signal
Output at finishing the transfer of first line display data.
Cycle of reversing output of M is able to be set by MT register.
OSC1 LCDENB
(4) Reset-1st line of 1st frame
RESET OSC1 LCDENB LP FLM M
1 2 3 4 5 6
"L"
CP
1st line of 1st frame (5) 1st line-2nd line
OSC1 LP FLM M
76 77 78 79 80
1
2
3
4
5
6
7
8
CP
1st line (6) 240th line of 1st frame-1st line of 2nd frame 2nd line
OSC1 LP FLM M
76 77 78 79 80 1 2 3 4 5 6 7 8
"L"
CP
240th line of 1st frame 1st line of 2nd frame
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 22 of 27
M66271FP
Timing Diagram
(1) Write to Control Register (RD = "H")
Without WAIT
tw (IOCS)
IOCS
tw (LWR)
LWR WAIT
"H"
tsu (D-IOCS)
tsu (D-LWR)
th (IOCS-D)
th (LWR-D)
D <7:0>
tsu (A-IOCS) tsu (A-LWR)
Data input is established
th (IOCS-A) th (LWR-A)
A <4:0>
Address is established
(2) Read from Control Register (LWR = "H")
Without WAIT
IOCS RD WAIT
ta (IOCS-D) ta (RD-D)
"H"
tdis (IOCS-D)
tdis (RD-D)
D <7:0>
tsu (A-IOCS) tsu (A-RD)
Data output is established
th (IOCS-A) th (RD-A)
A <4:0>
Address is established
Note: 1. Writing/Reading operation for the control register is performed during overlapping IOCS and (LWR or RD). Limits of IOCS, LWR and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 23 of 27
M66271FP (3) Write to VRAM (RD = "H")
Term of non cycle steal access
tw (MCS)
MCS
tw (WR)
LWR (+HWR) WAIT "H"
tsu (D-MCS) tsu (D-WR) th (MCS-D) th (WR-D)
D <7:0> (D <15:0>) A <13:0> (+BHE)
Data input is established
tsu (A-MCS) tsu (A-WR)
th (MCS-A) th (WR-A)
Address is established
(4) Read from VRAM (LWR, HWR = "H")
Term of non cycle steal access MCS RD WAIT
ta (MCS-D) ta (RD-D)
"H"
tdis (MCS-D) tdis (RD-D)
D <7:0> (D <15:0>)
Data output is established
tsu (A-MCS) tsu (A-RD) th (MCS-A) th (RD-A)
A <13:0>
Address is established
Note: 2. Writing/Reading operation for VRAM during non cycle steal access is performed during overlapping MCS and [LWR (+HWR) or RD]. Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 24 of 27
M66271FP (5) Write to VRAM (RD = "H")
Term of cycle steal access
tC (CLK)
tWH (CLK)
tWL (CLK)
MPUCLK
tw (MCS)
MCS
tw (WR)
LWR (+HWR) WAIT
tpHL (MCS-WAIT)
tpLH (CLK-WAIT)
tsu (D-MCS) tpHL (WR-WAIT)
tsu (D-WR)
th (MCS-D)
th (WR-D)
D <7:0> (D <15:0>)
A <13:0> (+BHE)
Data input is established
tsu (A-MCS)
tsu (A-WR)
th (MCS-A) th (WR-A)
Address is established
(6) Read from VRAM (LWR, HWR = "H")
Term of cycle steal access
tC (CLK) tWH (CLK) tWL (CLK)
MPUCLK
MCS RD WAIT
tpHL (MCS-WAIT) tpLH (CLK-WAIT)
tpHL (RD-WAIT) ta (MCS-D) ta (RD-D) tpd (D-WAIT)
tdis (MCS-D)
tdis (RD-D)
D <7:0> (D <15:0>)
A <13:0>
Data output is established
tsu (A-MCS)
tsu (A-RD)
th (MCS-A) th (RD-A)
Address is established
Notes: 3. Reading/writing operation for VRAM during cycle steal needs 1 tc (Internal) in best case or 3 tc (Internal) in worst case, according to the condition of the internal cycle steal at starting access requested from MPU. tc (Internal) = Clock cycle time after setting division of OSC1. Data output D in reading is established before changing WAIT to "H". 4. Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access. 5. Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as don't output next WAIT, this is cause of error action.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 25 of 27
M66271FP (7) Interface Timing with LCD (OSCC = 1 division: set) (When OSCC = 1 division, OSC clock for internal operation = OSC1 input.) 1. Transfer of LCD display data
tC (OSC) tWH (OSC) tWL (OSC)
OSC1
tpd (OSC-CP) tWH (CP) tC (CP) tWL (CP)
CP
tpLH (OSC-LP) tpHL (OSC-LP)
LP
ta (UD)
UD <3:0>
Data is indefinite
2. LCD control signal
OSC1 CP LP
tpLH (OSC-FLM)
tpHL (OSC-FLM)
FLM
tW (FLM)
tpd (OSC-M)
M
tpLH (OSC-LE) tpHL (OSC-LE)
LCDENB
Note: 6. Output signal to LCD side is synchronized with OSC clock for internal operation. When division is set to 1/2 to 1/16 by OSCC register, switching characteristics is defined by rising edge of OSC1.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 26 of 27
M66271FP
Package Dimensions
JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g
HD
*1
D 41
64
65
40
ZE
*2
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
HE
E
80 25
Reference Symbol
Dimension in Millimeters
1
ZD
24 Index mark F
c
D E A2 HD HE A A1 bp c
L Detail F
*3
REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 27 of 27
A1
e
y
bp
e y ZD ZE L
Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 0.8 1.0 0.4 0.6 0.8
A
A2
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